Binary communication systems represent information using just two symbols—e.g. relatively high and low voltages—to alternatively represent a logical one and a logical zero (i.e. 1b or 0b, where “b” is for binary). The number of levels used to represent digital data is not limited to two, however. For example, a type of signaling referred to as PAM-4 (for 4-level pulse-amplitude modulation) uses four separate pulse amplitudes (voltages) to convey two binary bits of data per symbol (i.e., 00b, 01b, 10b, or 11b). A series of symbols can thus be communicated as a voltage signal that transitions between levels in a manner that reflects the series. The time each voltage level is held to represent a symbol is termed the “symbol duration time” or “unit interval.” The speed with which symbols can be communicated is termed the “symbol rate,” which can be expressed in units of symbols per second, or “baud.” A receiver recovers a set of symbols from a signal by comparing the voltage during each symbol time against one or more reference-voltage levels to distinguish between symbols.
High-performance communication channels suffer from many effects that degrade symbols and consequently render them difficult to resolve. Primary among them are frequency dependent channel loss (dispersion) and reflections from impedance discontinuities. These effects cause neighboring symbols to interfere with one another and are commonly referred to collectively as Inter-Symbol Interference (ISI). For example, neighboring relatively high-voltage symbols may spread out to raise the level of neighboring lower-voltage symbols; the lower-voltage symbols may be interpreted incorrectly. Lower-voltage symbols may likewise induce errors in neighboring higher-voltage symbols.
ISI becomes more pronounced at higher symbol rates, ultimately degrading signal quality such that distinctions between originally transmitted symbols may be lost. Some receivers mitigate the effects of ISI using one or more equalizers. One common type of equalizer, the decision-feedback equalizer (DFE), corrects for ISI imposed on a “victim” symbol by a neighboring “aggressor” symbol by multiplying the value of the aggressor symbol by a “tap value” calibrated to account for the ISI and subtracting the resultant corrective from the victim's signal level. Thus, for example, ISI from a prior symbol that tends to raise or lower the level of the immediate symbol is offset by a similar and opposite change to the immediate symbol level, or by a similar offset in the reference against which the immediate symbol is interpreted.
Unfortunately, calibrating and maintaining a sufficient number of signal offsets or reference levels can be daunting. In a PAM-4 system, for example, each symbol is evaluated against three reference levels that collectively change depending upon the value of the preceding symbols. A one-tap DFE therefore provides twelve calibrated offsets or twelve calibrated reference levels to manage the impact of ISI. The requisite circuitry is complex, area intensive, and power hungry.
ISI calibration is but one difficulty. Sample timing is also critical, particularly at high symbols rates. Typically, a clock and data recovery (CDR) circuit aligns edges of a sampling clock signal with incoming data symbols. CDRs detect phase errors between the clock and data symbols and adjust the clock to minimize the phase errors. Modern systems, such as multi-chip modules, include large numbers of high-speed channels that require independent timing control. Power, area, and latency are therefore critical.